As means for forming a thin film on a substrate, for example, various film forming methods such as a sputtering method, a vacuum deposition method, or a chemical vapor deposition (CVD) method are generally used.
In a case where a chemical vapor deposition method is used, a high-quality film can be formed. In a case where the thickness and composition of a film to be formed, the concentrations of impurities to be added, and the like vary, the performance of a semiconductor device or the like changes. Therefore, in particular, a high-quality film is required, and as a method of forming such a semiconductor layer, a chemical vapor deposition method is generally used.
For example, as a substrate for forming a SiC epitaxial film in a SiC epitaxial wafer, a SiC single-crystal substrate which is obtained by processing bulk SiC single crystal prepared using a sublimation method is used. Typically, a SiC epitaxial film which forms an active region of a SiC semiconductor device is grown on the SiC single-crystal substrate using a chemical vapor deposition (CVD) method.
In a manufacturing process of the epitaxial wafer, smoothing a surface of the epitaxial wafer has been an issue for a long time. In order to increase the effective area of a wafer, it is not only required to increase the size of a wafer but also to reduce an edge exclusion zone (ineffective region surrounding a semiconductor wafer; typically, expressed by the distance from an edge).
In a case where the edge exclusion zone can be reduced, the effective area ratio which can be achieved in a semiconductor chip can be increased, and thus the yield of the semiconductor chip can be improved. Therefore, recently, it has been required to further reduce the width of the edge exclusion zone.
However, during crystal growth, even in a case where a wafer is mounted in a space under the same conditions, it is observed that the growth rate varies between the center and an outer peripheral portion of the wafer. It is known that, in a case where a single-crystal wafer is epitaxially grown, the formation of a so-called edge crown in which an outer peripheral portion of a wafer thickens occurs. This edge crown is required to be removed because it increases the width of the edge exclusion zone.
Here, “increasing the width of the edge exclusion zone” does not represent that the width increases merely due to a difference in the thickness of an outer peripheral portion in which an edge crown is formed. For example, in a case where an edge crown is formed on an upstream side of a step flow, this edge crown interferes with uniform gas supply. Therefore, in an epitaxial film of an epitaxial wafer, defects may occur due to various transfers or the like, and the presence of these defects may also cause an increase in the width of the edge exclusion zone.
In addition, this edge crown may break during transport and damage an epitaxial surface of a wafer, or may cause cracking during processing. Therefore, the edge crown is required to be removed.
In the related art, in order to remove an edge crown, an outer peripheral portion of a wafer is removed in advance during the growth of an edge crown so as to prevent the outer peripheral portion of the epitaxial wafer from thickening (for example, PTL 1). In addition, a formed edge crown is removed after epitaxial growth (for example, PTL 2).
In addition, in a chemical vapor phase growth device, typically, a wafer (substrate) on which an epitaxial film is grown is disposed in the center of a concave portion (for example, a countersunk portion) provided in a susceptor (substrate support member). At this time, generally, a difference in level between a wafer surface and a susceptor surface is reduced in order to prevent this difference from interfering with the gas flow (for example, PTL 3). To that end, during silicon epitaxial growth, the depth of the concave portion of the susceptor also changes depending on the thickness of a silicon wafer so as to reduce a difference in level between an upper surface of the susceptor and an upper surface of the silicon wafer (PTL 4).